|نویسنده: Keliu Shu , Edgar Sanchez-Sinencio||ISBN-10: 0387236686|
|ناشر: Springer||ISBN-13: 978-0387236681|
|ویرایش: ویرایش 2005||تاریخ انتشار: November12, 2004|
|تعداد صفحات: 216||رتبه فروش در سایت آمازون: #4,774,894 در دسته (See Top 100 )|
|فرمت کتاب: pdf||#836دردسته Semiconductors|
|کیفیت صفحات: اصلی||#1541دردسته Circuit Design|
خلاصه ای از کتاب:
Thanks to the advance of semiconductor and communication technology, the wireless communication market has been booming in the last two decades. It evolved from simple pagers to emerging third-generation (3G) cellular phones. In the meanwhile, broadband communication market has also gained a rapid growth. As the market always demands hi- performance and low-cost products, circuit designers are seeking hi- integration communication devices in cheap CMOS technology. The phase-locked loop frequency synthesizer is a critical component in communication devices. It works as a local oscillator for frequency translation and channel selection in wireless transceivers and broadband cable tuners. It also plays an important role as the clock synthesizer for data converters in the analog-and-digital signal interface. This book covers the design and analysis of PLL synthesizers. It includes both fundamentals and a review of the state-of-the-art techniques. The transient analysis of the third-order charge-pump PLL reveals its locking behavior accurately. The behavioral-level simulation of PLL further clarifies its stability limit. Design examples are given to clearly illustrate the design procedure of PLL synthesizers. A complete derivation of reference spurs in the charge-pump PLL is also presented in this book. The in-depth investigation of the digital CA modulator for fractional-N synthesizers provides insightful design guidelines for this important block.
توضیحات پشت جلد کتاب:
CMOS PLL Synthesizers: Analysis and Design presents both fundamentals and state of the art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is implemented in 0.35mm CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which elegantly tackle speed and integration bottlenecks of PLL synthesizer.
This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers.